`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/10/23 15:27:24
// Design Name: 
// Module Name: aludec
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module aludec(
	input wire[5:0] funct,
	input wire[5:0] aluop,
	output reg[7:0] alucontrol
    );
	always @(*) begin
	    case (aluop)
	        6'b001100: alucontrol <= 8'b00010001;  //andi
	        6'b001110: alucontrol <= 8'b00010011;  //xori
	        6'b001111: alucontrol <= 8'b00010101;  //lui
	        6'b001101: alucontrol <= 8'b00010010;  //ori
	        default: case(funct)
	            6'b100100: alucontrol <= 8'b00010001;  //and
	            6'b100101: alucontrol <= 8'b00010010;  //or
	            6'b100110: alucontrol <= 8'b00010011;  //xor
	            6'b100111: alucontrol <= 8'b00010100;  //nor
	            6'b000000: alucontrol <= 8'b00100001;  //sll
	            6'b000010: alucontrol <= 8'b00100010;  //srl
	            6'b000011: alucontrol <= 8'b00100011;  //sra
	            6'b000100: alucontrol <= 8'b00100100;  //sllv
	            6'b000110: alucontrol <= 8'b00100110;  //srlv
	            6'b000111: alucontrol <= 8'b00100111;  //srav
	            default: alucontrol <= 8'b00000000;
	        endcase
//		case (aluop)
//			2'b00: alucontrol <= 3'b010;//add (for lw/sw/addi)
//			2'b01: alucontrol <= 3'b110;//sub (for beq)
//			default : case (funct)
//				6'b100000: alucontrol <= 3'b010; //add
//				6'b100010: alucontrol <= 3'b110; //sub
//				6'b100100: alucontrol <= 3'b000; //and
//				6'b100101: alucontrol <= 3'b001; //or
//				6'b101010: alucontrol <= 3'b111; //slt
//				default:  alucontrol <= 3'b000;
//			endcase
		endcase
	end
endmodule
